1. Field of the Invention
Generally, the subject matter disclosed herein relates to integrated circuits, and, more particularly, to gate electrode structures of transistor devices formed by double exposure and double etch techniques.
2. Description of the Related Art
The fabrication of microstructures, such as integrated circuits, requires tiny regions of precisely controlled size to be formed in one or more material layers of an appropriate substrate, such as a silicon substrate, an SOI (silicon-on-insulator) substrate or other suitable carrier materials. These tiny regions of precisely controlled size are typically defined by patterning the material layer(s) by applying lithography, etch, implantation and deposition processes and the like, wherein, typically, at least in a certain stage of the patterning process, a mask layer may be formed over the material layer(s) to be treated to define these tiny regions. Generally, a mask layer may consist of or may be formed by means of a layer of resist that is patterned by a lithographic process, typically a photolithography process. During the photolithographic process, the resist may be spin-coated onto the substrate surface and then selectively exposed to ultraviolet radiation through a corresponding lithography mask, such as a reticle, thereby imaging the reticle pattern into the resist layer to form a latent image therein. After developing the photoresist, depending on the type of resist, positive resist or negative resist, the exposed portions or the non-exposed portions are removed to form the required pattern in the layer of photoresist. Based on this resist pattern, actual device patterns may be formed by further manufacturing processes, such as etching, implantation and the like. Since the dimensions of the patterns in sophisticated integrated microstructure devices are steadily decreasing, the equipment used for patterning device features have to meet very stringent requirements with regard to resolution and overlay accuracy of the involved fabrication processes. In this respect, resolution is considered as a measure for specifying the consistent ability to print minimum size images under conditions of predefined manufacturing variations. One important factor in improving the resolution is the lithographic process, in which patterns contained in the photo mask or reticle are optically transferred to the substrate via an optical imaging system. Therefore, great efforts are made to steadily improve optical properties of the lithographic system, such as numerical aperture, depth of focus and wavelength of the light source used.
The resolution of the optical patterning process may, therefore, significantly depend on the imaging capability of the equipment used, the photoresist materials for the specified exposure wavelength and the target critical dimensions of the device features to be formed in the device level under consideration. For example, gate electrodes of field effect transistors, which represent an important component of modern logic devices, may have a length of less than 50 nanometers (nm) in currently produced devices, with significantly reduced dimensions for device generations that are currently under development. Consequently, the actual feature dimensions may be well below the wavelength of currently used light sources provided in current lithography systems. For example, presently, in critical lithography steps, an exposure wavelength of 193 nm may be used, which, therefore, may require complex techniques for finally obtaining resist features having dimensions well below the exposure wavelength. Thus, highly non-linear processes are typically used to obtain dimensions below the optical resolution. For example, extremely non-linear photoresist materials may be used, in which a desired photochemical reaction may be initiated on the basis of a well-defined threshold so that weakly exposed areas may substantially not change at all, while areas having exceeded the threshold may exhibit a significant variation of their chemical stability with respect to a subsequent development process.
Consequently, significant advances and development of appropriate photoresist materials in combination with the progresses made in providing highly complex imaging tools may enable the printing of mask features having critical dimensions that are significantly less compared to the exposure wavelength used. Moreover, additional process techniques may be applied, which enable a further reduction of the resist features, thereby even further reducing the critical dimensions of circuit elements. For example, appropriate hard mask features may be formed on the basis of sophisticated trim etch techniques having a width of approximately 50 nm, thereby enabling the patterning of gate electrode structures having a gate length that substantially corresponds to the width of the mask features. Upon further reducing the overall dimensions of sophisticated semiconductor devices, not only the length of the gate electrode structure has to be reduced, for instance to 50 nm and less, but also the width of the gate electrode structures have to be reduced to several hundred nanometers and significantly less, in particular in densely packed device areas, such as static RAM areas in complex semiconductor devices. In addition, the tip-to-tip critical dimension from one gate to another has to be reduced in order to guarantee sufficient gate past active coverage such that the active area for maximum transistor drive currents can be enlarged.
Since critical lithography processes may be controlled more efficiently by printing resist features which have a critical dimension in one lateral direction only, it has been proposed to split the patterning process for providing appropriate resist features for sophisticated gate electrode structures into two steps in order to appropriately adjust the gate length, for instance on the basis of trim etch techniques, and the gate width, thereby allowing reduced transistor width, as is frequently required in critical device areas, such as RAM areas. It turns out, however, that upon further shrinkage of the overall device dimensions, the two-step patterning process for forming the mask features for the gate electrode structures may suffer from reduced scalability and controllability, as will be described in more detail with reference to FIGS. 1a-1j. 
FIG. 1a schematically illustrates a top view of a typical layout or an actual implementation of a semiconductor device 60, which may have to be formed on the basis of reduced transistor dimensions. As illustrated, the semiconductor device 60 may comprise active regions 62A, 62B, which are to be understood as semiconductor regions in and above which one or more transistors are to be formed. Typically, the active regions 62A, 62B are laterally delineated by an isolation structure or region 62C, such as a silicon dioxide region, and the like. Furthermore, a plurality of gate electrode structures 160 are provided above the active regions 62A, 62B in accordance with the general layout of the semiconductor device 60, as is, for instance, required in a densely packed device region. For example, the gate electrode structures 160 may comprise gate electrode structures 160A, 160B, 160C, 160D, which may have a gate length 160L that is typically 50 nm and less in sophisticated semiconductor devices. In densely packed device areas, the gate electrode structures 160, such as the gate electrode structures 160A, 160B, have to be provided with a minimum lateral off-set or pitch, which may by 60 nm and less, depending on the overall device requirements. As discussed above, typically, the width of corresponding transistors and thus the width, indicated by W, of the gate electrode structures 160 has to be reduced, thereby also requiring a lateral distance or off-set in the width direction, as indicated by 160P, which may be in the same order of magnitude as the gate length in sophisticated applications. For example, the lateral distance 160P may be selected so as to allow a certain overlap with the isolation region 62C while at the same time reliably isolating the various gate electrode structures from each other. Consequently, upon further reducing the overall dimensions, for example the width of the isolation structure 62C, the lateral distance 160P may also represent a very critical dimension in forming the gate electrode structures 160. Consequently, strategies have been proposed in which the gate length 160L may be defined by performing the first patterning process, followed by a further patterning process, in which the lateral distance 160P may be defined.
FIG. 1b schematically illustrates a top view of the device 60 when performing a two-step patterning process for forming the gate electrode structures 160 as shown in FIG. 1a. As illustrated, in this manufacturing stage, mask features 111A, 111B may be formed above the mask layer 16, which may represent any appropriate hard mask material, such as silicon dioxide, silicon nitride and the like, which may result in a significantly reduced etch rate compared to an actual gate electrode material, such as polysilicon and the like. The mask features 111A, 111B may be provided in the form of resist features, which may be obtained on the basis of sophisticated lithography techniques, in combination with any additional etch trim processes and the like, in order to determine the lateral size and position of the gate electrode structures 160, however, without determining the width thereof. This may be accomplished by a further lithography and patterning process, in which a mask opening may be formed in the mask layer 16, thereby “cutting” the gate electrode structures 160 defined by the size and position of the resist features 111A, 111B into gate electrode portions of a desired width, as is shown in FIG. 1a. A corresponding process for forming the mask features 111A, 111B and the mask opening and a subsequent patterning process for forming the actual gate electrode structures 160A . . . 160D (FIG. 1a) will now be described in more detail with reference to FIGS. 1c-1j. 
FIG. 1c schematically illustrates a perspective view of the semiconductor device 60 comprising a substrate 61, such as a silicon material, an SOI (silicon-on-insulator) substrate and the like. Furthermore, a semiconductor layer 62, such as a silicon layer, may be provided above the substrate 61 and may comprise a plurality of active regions and isolation structures, as is also described above with reference to FIG. 1a. Furthermore, a gate dielectric material 161, for instance in the form of silicon dioxide, silicon oxynitride and the like, is formed above the semiconductor layer 62, followed by an electrode material 162, such as a polysilicon material and the like. The mask layer 16, which may comprise a plurality of sub-layers, depending on process specifics and the like, is formed above the electrode material 162. Moreover, in the manufacturing stage shown, the mask features 111A, 111B are formed on the mask layer 16. For example, the mask features 111A, 111B may be comprised of a resist material.
The semiconductor device 60 as illustrated in FIG. 1c may be formed on the basis of the following process strategies. The semiconductor lay 62 may be patterned to receive appropriate isolation structures, such as the isolation region 62C of FIG. 1a, which may be accomplished by sophisticated lithography, etch, deposition and planarization techniques. In this manner, also any active regions in the semiconductor layer 62 may be laterally delineated and may be subsequently treated to adjust the desired basic transistor characteristics by incorporating an appropriate well dopant species and the like. Next, the gate dielectric material 161 may be formed, for instance by oxidation, deposition and the like, followed by the deposition of the electrode material 162, using well-established low pressure chemical vapor deposition (CVD) techniques and the like. Thereafter, the hard mask layer 16, which may comprise two or three sub-layers and the like, may be deposited on the basis of appropriate deposition techniques. For example, silicon dioxide, silicon nitride, amorphous carbon and the like may be efficiently used as hard mask materials. Next, an appropriate material system including a resist material may be formed and exposed by using sophisticated lithography techniques. The resist material may then be developed and further treated so as to adjust the desired gate length, as discussed above with reference to FIGS. 1a and 1b. To this end, well-established trim etch techniques may be applied. Consequently, the further processing may be continued on the basis of the resist features 111A, 111B, having the target gate length, while on the other hand, the width is still to be defined on the basis of a further lithography process.
FIG. 1d schematically illustrates the device 60 after an etch process for patterning the mask layer 16 on the basis of the resist features 111A, 111B. Consequently, corresponding mask features in the form of hard mask features 16A, 16B may be provided and may thus have a desired gate length. To this end, any well-established anisotropic etch techniques, such as reactive ion etching and the like, may be used.
FIG. 1e schematically illustrates the semiconductor device 60 after the removal of the mask features 111A, 111B (FIG. 1d). In this stage, the device 60 may be prepared for a further critical lithography process in order to “cut” the hard mask features 16A, 16B so as to have the desired target width.
FIG. 1f schematically illustrates the device 60 with a corresponding opening or trench 1120 formed in a material system 112, which may comprise a resist material, an anti-reflective coating (ARC) material in combination with a planarization material, as discussed above. Due to the aggressive scaling of transistor devices, the width of the trench, which may thus define the lateral distance 160P (FIG. 1a) may represent a critical dimension and may have to be provided at the limit of the solution capabilities of sophisticated lithography processes. Consequently, upon further device scaling, the width of the opening 1120 may not allow further reduction of the lateral distance 160P (FIG. 1a), unless significant efforts may be made, for instance for developing new resist materials, further improving the optical characteristics of the complex lithography systems, or implement specific etch techniques upon forming the opening and/or upon etching through the mask features 16A, 16B.
FIG. 1g schematically illustrates the semiconductor device 60 after forming a mask opening 160 on the basis of the opening 1120 (FIG. 1f) by etching through the exposed portions of the mask features 16A, 16B. In some conventional approaches, the above-indicated limitations upon forming the opening 1120 (FIG. 1f) may be overcome by applying sophisticated etch techniques in order to actually reduce the lateral size of the opening 1120, thereby also reducing the lateral distance 160P of FIG. 1a. For example, complex polymerization components may be added to the plasma-based etch chemistry in order to create a certain “deposition” behavior during the etch process at sidewalls of the openings 1120, thereby also reducing the lateral distance between isolated portions of the mask features 16A, 16B.
FIG. 1h schematically illustrates the device 60 after the removal of the material system 112 (FIG. 1g). Thus, as illustrated, a plurality of isolated mask features 16A, 16B, 16C and 16D are provided, which may have a desired gate length, for instance as defined by the resist features 111A, 111B of FIG. 1c, while the lateral distance 160P (FIG. 1a) may be obtained as defined by the opening 1120 of FIG. 1f. 
FIG. 1i schematically illustrates the semiconductor device 60 in a further advanced manufacturing stage, in which the plurality of gate electrode structures 160A, 160B, 160C and 160D are formed on the basis of any appropriate anisotropic etch technique, in which the mask features 16A, 16B, 16C and 16D are used as an efficient etch mask.
FIG. 1j schematically illustrates the semiconductor device 60 in a further advanced manufacturing stage, in which the gate dielectric material 161 is also patterned, which may be accomplished in a separate etch process on the basis of any well-established etch techniques.
Consequently, the arrangement of the isolated gate electrode structures 160A, 160B, 160C and 160D may be obtained on the basis of two different patterning sequences, each including a specific lithography process and an etch process in order to provide the hard mask features 16A, 16B, 16C and 16D, wherein the gate length may be determined on the basis of etch trim techniques, while, however, the lateral distance 160L (FIG. 1a) may be increasingly difficult to be implemented upon further device scaling. On the other hand, sophisticated etch techniques, for instance using polymerizing gases during the etch process for transferring the opening 112O (FIG. 1f) into the underlying mask features may result in significant device variations, while other approaches, such as improving the resist materials and/or the optical imaging system, may require significant research and development improvements and any such improvements are not yet available.
In US Patent Publication No. 2012/0049286, a different approach was suggested. According to the teachings of US 2012/0049286, the lateral dimensions of a mask opening are reduced by forming a spacer element on inner sidewalls thereof in order to determine the lateral dimensions of circuit features in one direction. Thereafter, appropriate mask features are formed above the underlying mask layer including the mask opening of reduced lateral dimensions. The mask opening defines a lateral separation of the mask features. On the other hand, the widths of the mask features that correspond to a desired gate length are adjusted by using any appropriate process technique, such as trim etch techniques. Consequently, upon transferring the mask features into the underlying mask layer, the desired lateral dimensions in both lateral directions may be obtained in the mask layer with a higher degree of controllability and superior uniformity compared to conventional strategies as described above. However, it turned out that the mask opening involved in the taught procedure may undesirably leave some imprint in the polysilicon layer of the gate electrode of a transistor. This imprint deteriorates the overall operation of the finished transistor/semiconductor device.
In view of the situation described above, the present disclosure relates to manufacturing techniques for semiconductor devices, in which circuit features, such as gate electrode structures with minimized tip-to-tip critical dimensions (distances) from one tip of a gate electrode to another tip of another gate electrode, may be formed, while alleviating one or more of the problems identified above.